Processor Core
System / Debug
Bus / Memory
I/O Peripherals
System Services
Clock / Reset

I'm building an ARM Cortex-M processor from scratch in SystemVerilog — no IP cores, just the architecture spec and a Zynq-7010. Each block here is something I've written and verified myself. Hopefully it boots up once everything is in place.

Toolchain: Xilinx Vivado  ·  Target: Zynq-7010 SoC FPGA

Click on each block to open on GitHub
ARM CORTEX-M · SYSTEM-ON-CHIP · FPGA IMPLEMENTATION PROCESSOR CORE 01 Pipeline 2-stage (M0/M0+) 3-stage (M3/M4) 6-stage OOO (M7) Thumb-only · In-order 02 ALU + Register File R0–R12, SP, LR, PC xPSR · HW Multiply SDIV / UDIV (M3+) Barrel shifter · Sat 03 Thumb/Thumb-2 Decoder 16-bit Thumb (M0/M0+) 16+32-bit T2 (M3+) IT block · CBZ/CBNZ TBB/TBH table branch 13 DSP + FPU SIMD MAC / SMLAD (M4+) FPv4-SP (M4) · FPv5 (M7) S0–S31 · D0–D15 (M7) Lazy FP stacking · FPSCR 12 Privilege + Modes Thread / Handler mode MSP / PSP banked SP CONTROL · PRIMASK EXC_RETURN mechanism 16 Clock + Power WFI / WFE · Sleep modes SLEEPDEEP · ONEXIT ICG · CDC · 2FF sync MMCM/PLL (FPGA) REGISTER BANK · xPSR {N,Z,C,V,Q,IT,T} · CONTROL · PRIMASK · FAULTMASK · BASEPRI Von Neumann (M0/M0+) · Modified Harvard (M3/M4/M7) · No ARM state · No MMU EXC_RETURN · 8-word auto-push on exception entry {xPSR, PC, LR, R12, R3, R2, R1, R0} SYSTEM CONTROL & DEBUG 06 NVIC 1–240 IRQs · up to 256 levels Tail-chaining · Late-arrival Vector table in SRAM / Flash ISER / ICER / ISPR / IPR BASEPRI · priority grouping Zero-latency IRQ option 18 SysTick 24-bit down-counter HCLK or external ref clock SYST_CVR · SYST_RVR RTOS tick source Auto-reload on zero COUNTFLAG bit 05 MPU 8 or 16 regions (M3+) RW / RO / XN attributes Cacheable / Shareable MPU_RBAR / MPU_RASR Sub-region disable (SRD) MemManage fault on violate 15 Debug — SWD / JTAG CoreSight DAP · SW-DP / JTAG-DP 6–8 HW breakpoints (FPB) 4 watchpoints (DWT) ITM trace · ETM (M7) SWO / TPIU / MTB Halt, step, reset, mem access 19 SCB — System Control Block CPUID · ICSR · VTOR AIRCR (reset / endian) CCR · SHPR1–3 CFSR / HFSR / MMFAR BFAR / AFSR / DFSR ACTLR · FPCCR / FPCAR BUS FABRIC I-CODE BUS (AHB-Lite) D-CODE BUS (AHB-Lite) AHB-LITE SYSTEM BUS APB PERIPHERAL BUS 07 AHB-Lite Single master · burst 32/64-bit data bus HREADY · HTRANS 08 AXI4-Lite 5-channel handshake Split R/W channels AHB → AXI bridge 09 APB Bridge AHB → APB translation Low-power peripherals PSEL · PENABLE · PREADY MEMORY SUBSYSTEM 04 Flash / SRAM / Cache Unified memory map · Bit-band I-cache / D-cache 4–64 KB (M7) TCM (ITCM/DTCM) · DTCM bus 17 Memory Map 0x00000000–0xFFFFFFFF (4 GB) 8 fixed 512 MB regions Bit-band 0x20000000 / 0x40000000 10 DMA Controller Multi-channel · M2M / M2P / P2M Priority · circular · burst AHB master · FIFO · double-buf 28 MMU Virtual → Physical translation TLB · 4 KB page granularity Page tables · access permissions I/O PERIPHERAL RING 20 Serial Interfaces UART · USART · SPI · I²C I²S · CAN · USB-FS / USB-HS LIN · SMBUS · SDIO / QSPI 21 Timers Advanced (TIM1/8) · GP · Basic PWM · Input capture · Encoder Dead-time · complementary out 22 Analog + GPIO 12-bit SAR ADC / 12-bit DAC Comparators · Opamp GPIO: push-pull / OD / AF / analog SYSTEM SERVICES 11 Exception / Vector Table 256 vectors · VTOR relocatable NMI · HardFault · SVC · PendSV Priority: -3 NMI, -2 HF, -1 Reset 14 Cache Maintenance Invalidate / Clean / Flush ops ICIALLU · DCCMVAC · DCCISW Cache by line / set / way (M7) 23 RTOS Support SysTick + PendSV preemption MSP/PSP dual stack · SVC gate BASEPRI masking · MPU isolation CLOCK, RESET & PERIPHERAL EXTENSION 24 Watchdog (WWDG / IWDG) WWDG: window, PCLK-clocked IWDG: LSI, independent 32 kHz Key register write-protect 25 EXTI Controller 23 configurable lines (STM32) Rising / Falling / Both edge Software interrupt · Wakeup 26 RCC — Reset & Clock Control Bus prescalers: AHB/APB1/APB2 Periph clock enable/disable regs Reset cause: POR/BOR/IWDG/SW 27 Clock Tree HSI / HSE / LSI / LSE oscillators PLL · MMCM (FPGA) BUFG · prescalers · glitch-free mux